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preliminary power psoc? device s cy8c42123/cy8c4222 3 cy8c42323/cy8c4242 3 cypress semiconductor corporation 198 champion court san jose , ca 95134 408.943.2600 document 38-12034 rev. *c revised november 17, 2005 1.0 features 1.1 key features extended operating voltage of 2.5v to 36v 2 hv linear opamp control loops for driving power pfets 2 hv switching control loops for driving external pfets 2 high voltage cmos or open drain outputs 2 high voltage analog sense inputs 4kb of flash 256 bytes of sram 1.2 improved features very low current mode for 100 na sleep (deep sleep) analog absolute accuracy (0.75%) additional flexibility for sleep modes 2 comparators with dac references 6- to 12-bit adc (20 ksps at 8 bits) configurable analog mux, 10:1 or 5:2 differential configurable digital blocks ? 8- to 16-bit timers, counters, and pwms ? connectable to all gpio pins ? connectable to all high voltage output pins ? single block deadband pwm with kill ? digital blocks can drive outputs to 36v ? complex peripherals by combining blocks 1.3 applications battery chargers (linear, switched, or fly back) dc-dc buck and boost converters fan controllers (tachometer, temp. sense, current limit) motor drivers (h-bridge, hall-effect sensors) white led drivers temperature sensor (thermistor, thermocouple) general-purpose high voltage microcontroller 2.0 block diagram figure 2-1. block diagram digital system 1 d ig ital row system bus system resources psoc core m8c cpu 256b sram 4kb flash gdo1 hvo[1] hvdd por and lvd system resets interrupt contr oller digital psoc block array dbc00 dbc01 dbd02 dbd03 psoc core internal voltag e reference low speed oscillator i2c digital clocks internal main oscillator global di gi tal interconnect bus atten0 atten1 am uxbus0 amuxbus1 am uxbus2 amuxbus3 p0[6] p0[4] p0[2] p0[0] p1[0] p0[7] p0[5] p0[3] p0[1] p1[1] odac0 odac1 vdac0 odac0 vbg ibias vdac0 vdac1 odac1 vdac1 vs1 gdo0 vs0 hvo[0] internal vdd analog and high voltage sections low drop-out regulator hv driver dbc01 dbc00 idac0 aclk comp1 aclk comp0 hv driver anal og to digital convertor sleep and watchdog idac1 vbg temp vr ef vss
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 2 of 42 3.0 complete feature list extended operating voltage of 2.5v to 36v powerful harvard architecture processor ? m8c processor speeds to 24 mhz ? low power at high speed ? industrial temperature range: -40c to +85c additional flexibility for sleep modes ? select when system resources are shut down ? very low current mode for 100 na sleep (deep sleep) 2 advanced power psoc blocks ? 2 high voltage analog sense inputs ? 2 high voltage linear opamp control loops for driving power pfets ? 2 high voltage switching control loops for driving ex- ternal pfets ? 2 high voltage cmos or open drain outputs advanced analog blocks ? analog absolute accuracy (0.75%) ? 2 comparators with dac references ? 6- to 12-bit adc (20 ksps at 8 bits) ? configurable analog mux, 10:1 or 5:2 differential 4 advanced digital blocks (2 with integrated deadband) ? 8- to 16-bit timers, counters, and pwms ? connectable to all gpio pins ? connectable to all high voltage output (hvo) pins ? single block deadband pwm with kill ? digital blocks can drive outputs to 36v ? complex peripherals by combining blocks flexible on-chip memory ? 4kb flash program storage 50,000 erase/write cycles ? 256 bytes sram ? in-system serial programming (issp ? ) ? partial flash updates (64-byte blocks) ? flexible protection modes ? eeprom emulation in flash precision, programmable clocking development tools ? free development software (psoc? designer) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128kb trace memory ? free application generation software (psoc express?) additional system resources ? i2c? master, slave, and multi-master to 400 khz ? watchdog and sleep timers ? user-configurable low voltage detection ? integrated supervisory circuit ? on-chip precision voltage reference ? 4-bit current references 4.0 psoc functional overview the key feature set of the power psoc family is the ability to be powered from and connect to voltages above the standard 5v logic voltage used by most microcontrollers. the power psoc's hv dd pin can connect to a supply voltage of up to 36v. internally, an ldo regulator converts the supply voltage to 5v for powering the analog system, digital system, the core, and the gpio. high voltage signals can be connected to the analog circuitry through one of two selectable attenuators, each having three ranges. these precision dividers reduce the external analog voltage by a factor of 4, 8, or 16. this allows single-ended or differential signals with up to 36v common mode to be measured with the adc. the gpio pins are not high-voltage tolerant. signals with voltages exceeding v gpio (as shown in the absolute maximum ratings table, table 8.2 ) cannot be connected to the gpio pins (p0 [7:0] and p1 [1:0]). doing so will damage the device. the power psoc family consists of several mixed-signal array with on-chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low-cost single-chip programmable component. a power psoc device includes configurable analog, digital, and power blocks, as well as programmable interconnects. this architecture allows the user to create customized peripheral configurations, to match the require- ments of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and config- urable io are included in a range of convenient pinouts. the psoc architecture, as illustrated in figure 2-1 , is comprised of five main areas: the core, the system resources, the digital system, the analog system, and the power control system. configurable global bus resources allow all the device resources to be combined into a complete custom system. each psoc device includes 4 digital blocks, up to 2 digital high voltage outputs, and up to 10 general purpose io (gpio). the gpio provide access to the global digital and analog interconnects. 4.1 power psoc core the power psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (internal main oscillator) and ilo (internal low-speed oscil- lator). the cpu core, called the m8c, is a powerful processor with speeds up to 24 mhz. the m8c is a four mips 8-bit harvard architecture microprocessor. system resources provide additional capability, such as digital clocks for increased flexibility of the psoc mixed-signal arrays; i2c functionality for implementing master, slave, and multi-master; an internal voltage reference of 1.3v for a number of analog psoc subsystems; and various system resets supported by the m8c.
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 3 of 42 4.2 digital system the digital system is composed of 4 digital psoc blocks, 2 enhanced basic (type d) and 2 basic (type c) to provide unique power control pulse width modulator (pwm) features. the power control features include integrated deadband, latched kill, and synchronous or asynchronous kill. the kill feature can be combined with a comparator to implement a fast over-current protection circuit. each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user module references. a sampling of digital block configura- tions is listed below. pwms (8 to 32 bit) pwms with deadband (8 to 16 bit) counters (8 to 32 bit) timers (8 to 32 bit) the digital blocks can be connected to any gpio (or digital high voltage output) through a set of global buses that can route any signal to any pin. the buses also allow signal multi- plexing and the combining of signals through logic operations. this configurability frees designs from the constraints of a fixed peripheral controller. 4.3 multiple sleep modes the cy8c42x23 devices can have some of the system resources (the sleeptimer/watchdog timer, the voltage regulator or the power supply supervisor) powered down in order to achieve the desired level of sleep current. sleep modes with current levels from 750 a in idle to 0.1 a in deep sleep, and wakeup times from instantaneous to 400 sec are available. deeper sleep modes have longer wakeup times and sleep modes with more resource power typically have shorter wakeup times. 4.4 analog system the cy8c42x23 devices have solid analog performance, low (100 v) offsets, reduced temperature sensitivity, and are capable of measuring 0.75% absolute voltage accuracy. the analog system is composed of configurable blocks to allow creation of complex analog signal flows. analog periph- erals are very flexible and can be customized to support specific application requirements. following are some of the more common psoc analog functions (most available as user modules). analog-to-digital converters (up to 12-bit resolution with single-ended or differential inputs). adjustable input gain of 1/4, 1, 4, or 16 for the adc. pin-to-pin comparator with low power mode for operation during sleep. single-ended or differential comparators (up to 2) with absolute (1.3v) reference or internal dac reference. 1.3v reference (as a system resource). 4.5 high voltage interface two types of high voltage outputs are available. hvo[0] and hvo[1] are digital outputs that can each be configured as a cmos output connected between hv dd and vss, or configured as an open-drain drive that can be externally pulled up to hv dd or down to vss. the second type, gate drive outputs (gdo0 and gdo1), can each be used to drive the gate of a high-side pfet in a linear or switched regulator. the gdo0 and gdo1 outputs will drive between hv dd -5v and hv dd , the signal level required for a "logic level" pfet. the gate drive outputs can be driven by an amplifier and used to control a pfet in a linear mode. a sense voltage can be fed back to the amplifier through an hv attenuator to implement a constant voltage or constant current driver. the output of the vdac can be used to set the target voltage of the regulator. alternately, the gate drive outputs can be connected to the output gated pwm and used to drive a pfet as a high-side switch in a boost or buck convertor. figure 4-1. analog block diagram gdo1 h vo[1] atten0 atten1 amuxbus0 amuxbus1 amuxbus2 amuxbus3 p0[6] p0[4] p0[2] p0[0] p1[0] p0[7] p0[5] p0[3] p0[1] p1[1] odac0 odac1 vdac0 odac0 vbg ibias vdac0 vdac1 odac1 vdac1 vs1 gdo0 vs0 hvo[ 0] analog and high voltage sections hv driver dbc01 dbc00 idac0 aclk comp1 aclk comp0 hv driver analog to digital convertor idac1 vbg temp vref vss
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 4 of 42 4.6 analog multiplexer system the analog mux bus can connect to every gpio pin in ports p0 and p1. pins can be connected to the bus individually or in any combination. the bus also connects to the analog sys- tem for analysis with comparators and analog-to-digital con- verters. this bus is split into four sections, amux bus 0 and amux bus 2, which connect to the even port pins and amux bus 1 and amux bus 3, which connect to the odd port pins. the four sections can be combined to support dual-channel single-end processing, single-channel differential processing, or dual-channel differential processing. they can also be connected as one bus that can route to all gpio pins. other multiplexer applications include: chip-wide mux that allows analog input from up to 10 gpio pins. crosspoint connection between any gpio pin combina- tions. 4.7 additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems implemented in a single power block. additional resources include an i2c master and slave, low voltage detection, and power on reset. brief statements describing the merits of each system resource are presented below. digital clock dividers provide three customizable clock frequencies for use in applications. the clocks can be routed to both the digital and analog systems. additional clocks can be generated using digital psoc blocks as clock dividers. the i2c module provides 50-, 100-, and 400-khz commu- nication over two wires. slave, master, and multi-master modes are all supported. low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.3 voltage reference provides an absolute reference for the analog system, including adcs and dacs. 4.8 development tools standard cypress psoc ide tools are available for debugging the cy8c42x23 family of parts. however, the additional trace length and a minimal ground plane in the flex-pod can create noise problems that make it difficult to debug a power psoc design. a custom bonded on-chip debug (ocd) device is available in an 32-pin qfn package. the ocd device is recommended for debugging designs that have high current and/or high analog accuracy require- ments. the qfn package is compact and can be connected to the ice through a high density connector. in-system serial programming (issp) is available. however, issp for power psoc differs from issp for standard psoc devices. with power psoc devices, the power pin (hv dd ) should not be connected directly to the v dd pin of the issp connector. doing so can damage the programming device.
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 5 of 42 5.0 typical power psoc applications 5.1 boost converter white led driver a white led driver is a constant current power supply. by driving the same current through a set of leds in series, the intensi ty of the leds can be closely matched. the cy8c42x23 power psoc can be configured as a constant voltage or constant current boost supply. in this configuration, the hv dd voltage is lower than required to drive the leds in series and a higher voltage must be generated. white leds typically have a forward voltage of around 4v, so in the five led configuration shown in figure 5-1 the led drive voltage would have to be around 20v (plus allowance for the voltage losses in the fet and the current sense resistor, r isense ). figure 5-1 shows an inductor, an nfet, a diode, and a capacitor configured as a boost converter with the cy8c42x23 as the controller. the voltage on the capacitor is fed back through a voltage sense pin, vs0, and an attenuator, atten0, to the compar ator, comp0. the vs0 pin can be connected directly to a voltage higher than hv dd , so no external signal level conversion is needed. the output of the comparator controls a single psoc digital bloc k configured as a pwm. the reference for the comparator is the output of vdac0. when the attenuator output exceeds the reference, the comparator will stop the pwm using the "kill" input. this creates a feedback loop that maintains the vs0 node at a voltage proportional to the vdac0 setting. the atten0 output is also connected to the adc so the control software can monitor the output voltage. to maintain constant current, the voltage across the r isense resistor is routed through pin p0[4] and amuxbus0 to the adc where it is monitored. the control software adjusts the vdac0 setting, based on current sense measurements, to achieve the desired current through the load. 5.1.1 resources this application could connect the r isense resistor to any of the gpio pins (p0[7:0] and p1[1:0]). the power psoc still has three digital blocks, half of the high voltage resources, one vdac, two idacs, seven of the analog multiplexer channels to the adc, and over 90% of the cpu available for other tasks. figure 5-1. boost converter white led driver gdo1 hvo[1] atten0 atten1 amuxbus0 am uxbus1 amuxbus2 am uxbus3 p0[6] p0[4] p0[2] p0[0] p1[0] p0[7] p0[5] p0[3] p0[1] p1[1] odac0 odac1 vdac0 odac0 vbg ibias vd ac 0 vdac1 odac1 vdac1 vs1 gdo0 vs0 hvo[0] hv driver dbc01 dbc00 idac0 aclk comp1 aclk comp0 hv driver analog to digital convertor id ac 1 hvdd r isense hvdd internal vdd analog and high voltage sections low dr op-out regulator hvdd vbg temp vref vss pwm db dcb00 dcb01 kill pwm primary digital section dbd02 dcd03 q1
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 6 of 42 5.2 buck converter battery charger with current limit a battery charger is constant current and constant voltage power supply. at different points in a charging cycle a lithium ion battery requires a constant current or a constant voltage to be applied. the cy8c42x23 power psoc can be configured as a constant voltage or constant current linear supply. in this configuration, the hv dd voltage is high enough to drive one or more battery in series and a lower voltage must be generated efficiently. lithium ion batteries have a fully charged voltage of 4.2v . with the two-cell configuration in figure 5-2 , hv dd would have to be at least 8.4v (plus allowance for voltage losses in the fet and the current sense resistor, r isense ). the hv dd voltage is converted to 5v by the internal low drop-out regulator for use by the power psoc core. figure 5-2 shows an inductor, two fets, and a capacitor configured as a buck converter with the cy8c42x23 as the controller. the voltage on the capacitor is fed back through a voltage sense pin, vs1, and an attenuator, atten1, to the comparator, comp1. the output of the comparator controls a single psoc digital block configured as a pulse width modulator (pwm). the reference for the comparator is the output of vdac1. when the attenuator output exceeds the reference, the comparator will stop the pwm using the "kill" input. this creates a feedback loop that maintains the vs1 node at a voltage proportional to the vdac1 setting . the atten1 output is also connected to the adc so the control software can monitor the output voltage. the accuracy of the adc and the control loop are better than 0.75%. meeting high accuracy is critical to lithium ion batteries. to maintain constant current, the voltage across the r isense resistor is routed through pin p1[0] and amuxbus0 to the adc where it is monitored. the control software adjusts the vdac1 setting, based on current sense measurements, to achieve the desired current through the load. the current sense voltage is also connected to the positive input of comp0. the negative inpu t of comp0 is controlled by the output of odac0. if the current sense voltage exceeds the odac0 setting, the output of the comparator will be latched high. this acts as an over-current detection circuit that can be cleared by the control software. th e output of the comparator, comp0, can be combined with the output of comp1 and connected to the kill input of the pwm. this configures the power psoc so that an over-current condition will shut off the external pfet. for a lower cost, but lower efficiency, converter, q2 can be replaced with a diode. 5.2.1 resources this application could connect the r isense resistor to any of the gpio pins (p0[7:0] and p1[1:0]). the power psoc still has three digital blocks, half of the high voltage resources, one vdac, two idacs, seven of the analog multiplexer channels to the adc, and over 90% of the cpu available to implement the battery charging algorithm and other tasks. figure 5-2. buck converter battery charger with current limit gdo1 hvo[1] atten0 atten1 am uxbus0 amuxbus1 amuxbus2 amuxbus3 p0[6] p0[4] p0[2] p0[0] p1[0] p0[7] p0[5] p0[3] p0[1] p1[1] odac0 odac1 vdac0 odac0 vbg ibias vdac0 vdac1 odac1 vdac1 vs1 gdo0 vs0 hvo[0] hv driver dbc01 dbc00 idac0 aclk comp1 aclk comp0 hv driver analog to digital conver tor idac1 hvdd r isense hvdd internal vdd analog and high voltage sections low drop-out regulator hvdd vbg temp vref vss pwm db dcb00 dcb01 ki ll pwm pr imar y digital section dbd02 dcd03 pwm secondar y q1 q2
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 7 of 42 5.3 brushless dc fan motor the cy8c42x23 psoc can be configured as a one- or two-phase brushless dc motor controller suitable for use in small brushless fans. in this configuration, the hv dd voltage is high enough to drive a one- or two-phase brushless motor coil, typically 12v. the hv dd voltage is converted to 5v by the internal low drop-out regulator for use by the power psoc core. additionally, several milliamperes of 5v from the internal regulator is made available to bias a hall sensor and thermistor. the high side pfets of t he h-bridge are driven by the gdo0 and gdo1 pins controlled by the processor. the low side nfets of the h-bridge are driven by the hvo[0] and hvo[1] pins controlled by a combination of the processor and the pulse width modulator (pwm) for speed control. a differential comparator is used to determine rotor position from either an analog or digital hall sensor to facilitate rotor commu- tation. a second comparator and 8-bit dac, vdac0, are available to provide an optional hardware current limit. the 10-bit adc is available to measure optional parameters such as ambient temperature or motor coil current. the m8c processor handles coil commutation, user customizable speed, and control algorithms as well as an optional communications interface. the psoc digital resources provide an 8-bit pwm output to drive the motor coil as well as two timer configurations. using dynamic reconfiguratio n, two digital blocks are used to create a 16-bit timer to measure the tachometer period while the same two blocks are also used t o create two 8-bit timers to measure the input pwm duty cycle. 5.3.1 resources this application leaves 3 gpio pins, 1 digital block, i2c and ample memory unused for further application customization. figure 5-3. brushless dc fan motor pwm db gdo1 vss atten0 atten1 temp amuxbus0 amuxbus1 amuxbus2 amuxbus3 p0[6] p0[4] p0[2] p0[0] p1[0] p0[7] p0[5] p0[3] ` p1[1] odac0 vref avdd vbg odac1 vdac0 odac0 vbg ibias vdac0 vdac1 odac1 vdac1 vs1, hvo[1] gdo0 vs0, hvo[0] dbc01 dbc00 idac0 aclk comp1 aclk comp0 analog to digital convertor idac1 kill hvdd inter nal vdd analog and high voltage sections low dr op-out regulator hvdd r isense hvdd analog hall sensor 5v p0[1] 5v t 16-bit timer (tachometer) 2x8-bit timer (input pwm) pwm out capture input pwm tach out optional optional 5v out digital section 1 or 2 phase brushless motor (1 phase depicted) hv driver hv driver
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 8 of 42 6.0 pin assignment this section lists, describes, and illustrates all power psoc device pins and pinout configurations. for up-to-date ordering, p inout, and packaging information, refer to the individual psoc device?s data sheet or go to http://www.cypress.com/psoc. 6.1 pinouts the psoc devices are available in a variety of packages. refer to the following information for details on individual devices. every port pin (labeled with a ?p?) in the following tables and illustrations is capable of digital io. 6.1.1 8-pin soic part pinouts the 8-pin soic part is for the cy8c42123 psoc device. 8-pin part pinout (soic) pin no. digital analog name description cy8c42123 psoc device 1 hvo hvo gd1 high side gate driver 1 2 io i p0[1] 3 io i p1[1] i2c clock* 4 power vss ground connection 5 io i p1[0] i2c data* 6 io i p0[0] 7 hvo hvi vs0 high voltage sense 0, high voltage out- put 0 8 power hv dd supply voltage legend i = input 5v only, o = output 5v only, hv = high voltage. * these are the issp pins, which are not highz at por (power on reset). see the power psoc mixed-signal array technical reference manual for details. soic 1 2 3 4 8 7 6 5 hvo[0], vs0 p0[0] p1[0] i2c* gd1 p0[1] i2c* p1[1] vss hv dd
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 9 of 42 6.1.2 16-pin soic part pinouts the 16-pin soic part is for the cy8c42223 psoc device. 16-pin part pinout (soic) pin no. digital analog name description cy8c42223 psoc device 1 hvo hvo gd1 high side gate driver 1 2 hvi vs1 high voltage sense 1 3 hvo hvo[1] high voltage output 1 4 io i p0[7] i2c clock 5 io i p0[5] i2c data 6 io i p0[3] 7 io i p1[1] i2c clock* 8 power vss ground connection 9 io i p1[0] i2c data* 10 io i p0[2] optional external clk input (extclk) 11 io i p0[4] 12 io i p0[6] optional external voltage reference (extref) 13 hvo hvo[0] high voltage output 0 14 hvi vs0 high voltage sense 0 15 hvo hvo gd0 high side gate driver 0 16 power hv dd supply voltage legend i = input 5v only, o = output 5v only, hv = high voltage. * these are the issp pins, which are not highz at por (power on reset). see the power psoc mixed-signal array technical reference manual for details. soic hv dd gd0 vs0 hvo[0] p0[6], extref p0[4] p0[2], extclk p1[0] i2c* 16 15 14 13 12 11 1 2 3 4 5 6 7 8 gd1 vs1 hvo[1] scl, p0[7] sda, p0[5] p0[3] i2c* p1[1] vss 10 9
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 10 of 42 6.1.3 16-pin tssop part pinouts the 16-pin tssop part is for the cy8c42323 psoc device. 16-pin part pinout (tssop) pin no. digital analog name description cy8c42323 psoc device 1 hvo hvo gd1 high side gate driver 1 2 hvo hvi vs1 high voltage sense 1, high voltage out- put 1 3 io i p0[7] i2c clock 4 io i p0[5] i2c data 5 io i p0[3] 6 io i p0[1] 7 io i p1[1] i2c clock* 8 power vss ground connection 9 io i p1[0] i2c data* 10 io i p0[0] 11 io i p0[2] optional external clk input (extclk) 12 io i p0[4] 13 io i p0[6] optional external voltage reference (extref) 14 hvo hvi vs0 high voltage sense 0, high voltage out- put 0 15 hvo hvo gd0 high side gate driver 0 16 power hv dd supply voltage legend i = input 5v only, o = output 5v only, hv = high voltage. * these are the issp pins, which are not highz at por (power on reset). see the power psoc mixed-signal array technical reference manual for details. tssop hv dd gd0 vs0, hvo[0] p0[6], extref p0[4] p0[2], extclk p0[0] p1[0] i2c* 16 15 14 13 12 11 1 2 3 4 5 6 7 8 gd1 hvo[1], vs1 scl, p0[7] sda, p0[5] p0[3] i2c* p1[1] vss 10 9 p0[1]
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 11 of 42 6.1.4 32-pin qfn part pinouts the 32-pin qfn part is for the cy8c42423 psoc device. important note for information on the preferred dimensions for mounting qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . 32-pin part pinout (qfn**) pin no. digital analog name description cy8c42423 psoc device 1 nc no connection 2hvo hvo[1] high voltage output 1 3 nc no connection 4 nc no connection 5 io i p0[7] i2c clock 6 io i p0[5] i2c data 7 io i p0[3] 8 io i p0[1] 9 nc no connection 10 nc no connection 11 io i p1[1] i2c clock* 12 power vss 13 io i p1[0] i2c data* 14 nc no connection 15 nc no connection 16 nc no connection 17 io i p0[0] 18 io i p0[2] optional external clk input (extclk) 19 io i p0[4] 20 io i p0[6] optional external voltage reference (extref) 21 i xres external reset 22 nc no connection 23 nc no connection 24 hvo hvo[0] high voltage output 0 25 dnu do not use 26 hvi vs0 high voltage sense 0 27 hvo hvo gd0 high side gate driver 0 28 power hv dd supply voltage 29 power hv dd supply voltage 30 hvo hvo gd1 high side gate driver 1 31 hvi vs1 high voltage sense 1 32 nc no connection cp power vss center pad must be connected to ground legend i = input 5v only, o = output 5v only, hv = high voltage, nc = no connection. * these are the issp pins, which are not highz at por (power on reset). see the power psoc mixed-signal array technical reference manual for details. **the qfn package has a center pad (cp) that must be connected to ground (vss). nc hv o[1] nc nc p0 [7 ] p0 [5 ] qfn (top view ) (cp) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 nc vs1 hvdd hvdd gd0 vs0 dnu p0 [3 ] p0 [1 ] hv o[0] nc p0[2] p0[0] nc nc i2c*, p1[1] vss i2c*, p1[0] nc nc nc nc xres p0[6] p0[4] gd1
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 12 of 42 the 32-pin qfn part is for the cy8c42000 on-chip debug (ocd) psoc device. note this part is only used for in-circuit debugging. it is not available for production . 32-pin ocd part pinout (qfn**) pin no. digital analog name description cy8c42000 ocd psoc device not for production 1 nc no connection 2hvo hvo[1] high voltage output 1 3ocd hclk on-chip debug clock 4ocd cclk on-chip debug clock 5 io i p0[7] i2c clock 6 io i p0[5] i2c data 7 io i p0[3] 8 io i p0[1] 9 nc no connection 10 nc no connection 11 io i p1[1] i2c clock* 12 power vss 13 io i p1[0] i2c data* 14 nc no connection 15 nc no connection 16 nc no connection 17 io i p0[0] 18 io i p0[2] optional external clk input (extclk) 19 io i p0[4] 20 io i p0[6] optional external voltage reference (extref) 21 i xres external reset 22 nc no connection 23 nc no connection 24 hvo hvo[0] high voltage output 0 25 dnu do not use 26 hvi vs0 high voltage sense 0 27 hvo hvo gd0 high side gate driver 0 28 power hv dd supply voltage 29 power hv dd supply voltage 30 hvo hvo gd1 high side gate driver 1 31 hvi vs1 high voltage sense 1 32 nc no connection cp power vss center pad must be connected to ground legend i = input 5v only, o = output 5v only, hv = high voltage, nc = no connection, ocd = on-chip debug. * these are the issp pins, which are not highz at por (power on reset). see the power psoc mixed-signal array technical reference manual for details. **the qfn package has a center pad (cp) that must be connected to ground (vss). nc hv o[1] hclk cclk p0 [7 ] p0 [5 ] qfn (top view ) (cp) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 nc vs1 hvdd hvdd gd0 vs0 dnu p0 [3 ] p0 [1 ] hv o[0] ocde p0[2] p0[0] nc nc i2c*, p1[1] vss i2c*, p1[0] nc nc nc ocdo xres p0[6] p0[4] gd1
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 13 of 42 7.0 registers this section discusses the registers of the power psoc device. it lists all the registers in mapping tables, in address order. 7.1 register conventions the register conventions specific to this section are listed in the following table. convention description r read register or bit(s) w write register or bit(s) l logical register or bit(s) c clearable register or bit(s) # access is bit specific
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 14 of 42 7.2 register map bank 0 table: user space name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access name addr (0,hex) access prt0dr 00 rw 40 80 c0 prt0ie 01 rw 41 81 c1 prt0gs 02 rw 42 82 c2 prt0dm2 03 rw 43 83 c3 prt1dr 04 rw 44 asc00cr0 84 rw c4 prt1ie 05 rw 45 asc00cr1 85 rw c5 prt1gs 06 rw 46 asc00cr2 86 rw c6 prt1dm2 07 rw 47 asc00cr3 87 rw idac_d c7 rw hvp2_dr 08 rw 48 asc01cr0 88 rw p0_mux c8 rw 09 49 asc01cr1 89 rw p1_mux c9 rw 0a 4a asc01cr2 8a rw ca 0b 4b asc01cr3 8b rw cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 d0 11 51 91 d1 12 52 92 d2 13 53 93 d3 14 54 94 d4 15 55 95 d5 16 56 96 i2c_cfg d6 rw 17 57 97 i2c_scr d7 # 18 58 98 i2c_dr d8 rw 19 59 99 i2c_mscr d9 # 1a 5a 9a int_clr0 da rw 1b 5b 9b int_clr1 db rw 1c 5c 9c int_clr2 dc rw 1d 5d 9d int_clr3 dd rw 1e 5e 9e int_msk3 de rw 1f 5f 9f int_msk2 df rw dbc00dr0 20 r ac0_mux 60 rw pwr0_cr a0 rw int_msk0 e0 rw dbc00dr1 21 w ac0_cr0 61 rw pwr1_cr a1 rw int_msk1 e1 rw dbc00dr2 22 rw ac0_cr1 62 rw a2 int_vc e2 rc dbc00cr0 23 rw ac0_cr2 63 rw a3 res_wdt e3 w dbc01dr0 24 r ac0_msp 64 rw aa_ref a4 rw e4 dbc01dr1 25 w ac0_lsp 65 rw a5 e5 dbc01dr2 26 rw ac0_msr 66 rw a6 e6 dbc01cr0 27 rw ac0_lsr 67 rw vdac_cr a7 rw e7 dbd02dr0 28 r ac0_cc 68 # vdac_dr0 a8 rw e8 dbd02dr1 29 w 69 vdac_dr1 a9 rw e9 dbd02dr2 2a rw 6a aa ea dbd02cr0 2b rw 6b ab eb dbd03dr0 2c r tmp_dr0 6c rw ac ec dbd03dr1 2d w tmp_dr1 6d rw ad ed dbd03dr2 2e rw tmp_dr2 6e rw ae ee dbd03cr0 2f rw tmp_dr3 6f rw af ef 30 cmp_syn 70 rw rdi0ri b0 rw f0 31 cmp_lfn0 71 rw rdi0syn b1 rw f1 32 72 rdi0is b2 rw f2 33 cmp_lmd 73 rw rdi0lt0 b3 rw f3 34 cmp_cds 74 rw rdi0lt1 b4 rw f4 35 cmp_cis 75 rw rdi0ro0 b5 rw f5 36 cmp_rdc 76 rw rdi0ro1 b6 rw f6 37 cmp_goen0 77 rw rdi0gf b7 rw cpu_f f7 rl 38 78 b8 f8 39 cmp_clk 79 rw b9 f9 3a cmp_cr 7a rw ba fa 3b cmp_src 7b rw bb fb 3c cmp_mux0 7c rw bc fc 3d cmp_mux1 7d rw bd cpu_scr2 fd rsw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed.
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 15 of 42 7.3 register map bank 1 table: configuration space name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access name addr (1,hex) access prt0dm0 00 rw 40 80 c0 prt0dm1 01 rw 41 81 c1 prt0ic0 02 rw 42 82 c2 prt0ic1 03 rw 43 83 c3 prt1dm0 04 rw 44 84 c4 prt1dm1 05 rw 45 85 c5 prt1ic0 06 rw 46 86 c6 prt1ic1 07 rw 47 87 idac_cr c7 rw hvp2_dm0 08 rw 48 88 c8 hvp2_dm1 09 rw 49 89 c9 hvp2_ds0 0a rw 4a 8a ca 0b 4b 8b cb 0c 4c 8c cc 0d 4d 8d cd 0e 4e 8e ce 0f 4f 8f cf 10 50 90 gdi_o_in d0 rw 11 51 91 gdi_e_in d1 rw 12 52 92 gdi_o_ou d2 rw 13 53 93 gdi_e_ou d3 rw 14 54 94 ac0_goen d4 rw 15 55 95 d5 16 56 96 d6 17 57 97 d7 18 58 98 ac0_clk d8 rw 19 59 99 d9 1a 5a 9a da 1b 5b 9b db 1c 5c 9c dc 1d 5d 9d osc_go_en dd rw 1e 5e 9e osc_cr4 de rw 1f 5f 9f osc_cr3 df rw dbc00fn 20 rw 60 slp_cr0 a0 rw osc_cr0 e0 rw dbc00in 21 rw 61 slp_cr1 a1 rw osc_cr1 e1 rw dbc00ou 22 rw 62 slp_cr2 a2 rw osc_cr2 e2 rw 23 63 a3 vlt_cr e3 rw dbc01fn 24 rw 64 bus_top a4 rw vlt_cmp e4 r dbc01in 25 rw 65 a5 e5 dbc01ou 26 rw 66 a6 e6 27 67 a7 e7 dbd02fn 28 rw 68 vdac_tr a8 rw imo_tr e8 w dbd02in 29 rw 69 vdac_itrip0 a9 rw lso_tr e9 rw dbd02ou 2a rw 6a aa bdg_tr ea rw 2b 6b ab eb dbd03fn 2c rw tmp_dr0 6c rw rdiv0 ac rw ec dbd03in 2d rw tmp_dr1 6d rw ad aa_tr ed rw dbd03ou 2e rw tmp_dr2 6e rw ae ee 2f tmp_dr3 6f rw af ef 30 70 rdi0ri b0 rw f0 31 71 rdi0syn b1 rw f1 32 72 rdi0is b2 rw f2 33 73 rdi0lt0 b3 rw f3 34 74 rdi0lt1 b4 rw f4 35 75 rdi0ro0 b5 rw f5 36 76 rdi0ro1 b6 rw f6 37 77 rdi0gf b7 rw cpu_f f7 rl 38 78 b8 f8 39 79 b9 f9 3a 7a ba fa 3b 7b bb fb 3c 7c bc fc 3d 7d bd cpu_scr2 fd rsw 3e 7e be cpu_scr1 fe # 3f 7f bf cpu_scr0 ff # blank fields are reserved and should not be accessed.
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 16 of 42 8.0 electrical specifications specifications are valid for -40 o c t a 85 o c and t j 100 o c, except where noted. 8.1 frequencies refer to table 8.4 for the electrical specifications on the internal main oscillator (imo) using slow imo (slimo) mode, which ca n be set using the cpu_scr1 register. figure 8-1a. supply voltage versus cpu frequency figure 8-1b. imo frequency trim options 36 4.75 3.00 93 khz 12 mhz 24 mhz cpu frequency hv dd voltage 36 4.75 3.00 93 khz 12 mhz 24 mhz im o frequency hv dd voltage 3.60 6 mhz slimo mode = 0 slimo mode=0 2.40 slimo mode=1 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slimo mode=0 ~ ~ ~ ~ ~ ~ ~ ~ 8.2 absolute maximum ratings a parameter description conditions min. typ. max. units t stg storage temperature higher storage temperatures will reduce data retention time. -50 ? +100 o c t a ambient temperature with power applied -40 ? +85 o c hv dd supply voltage on hv dd relative to vss -0.5 ? +40 v v gpio dc input to any low voltage input pin hv dd 5.0v. -0.5 ? hv dd + 0.5 v v gpio36 dc input to any low voltage input pin hv dd > 5.0v. -0.5 ? 5.5 v v gd dc input to any gate drive pin hv dd - 5.5 ? hv dd + 0.5 v v vs dc input to high voltage sense pin -0.5 ? hv dd + 0.5 v hvo dc applied to high voltage outputs in high-z state -0.5 ? hv dd + 0.5 i mio maximum current into any low voltage port pin -25 ? +50 ma i miohv maximum current into any high voltage port pin -50 ? +50 ma
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 17 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. i miogd b maximum current into any gate drive pin -10 ? 10 ma esd electro static discharge voltage human body model esd. 2000 ? ? v esd hv electro static discharge to high voltage port pin human body model esd. 2000 ? ? v lu latch-up current ? ? 200 ma a. operation at these conditions degrades reliability. b. cannot result in pin voltage exceeding v gd limits or thermal specifications being exceeded. 8.3 operating temperature parameter description conditions min. typ. max. units t a ambient temperature -40 ? +85 o c t j junction temperature the temperature rise from ambient to junction is package specific. see table 9.1, ?thermal impedances per package,? on page 38. the system designer must limit the power consumption to comply with this requirement. -40 ? +100 o c 8.4 dc chip-level specifications parameter description conditions min. typ. max. units hv dd supply voltage see table 8.18, ?dc por and lvd specifications,? on page 25. 2.5 ? 36 v i dd supply current, imo = 24 mhz conditions are hv dd = 5.0v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. ? 3 4 ma i dd36 supply current, imo = 24 mhz conditions are hv dd = 36v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. ? 3 4 ma i dd3 supply current, imo = 6 mhz conditions are hv dd = 3.3v, t a = 25 o c, cpu = 3 mhz, sysclk doubler disabled, vc1 = 1.5 mhz, vc2 = 93.75 khz, vc3 = 93.75 khz, analog power = off. slimo mode = 0. imo = 24 mhz. ? 1.2 2 ma 8.2 absolute maximum ratings a (continued)
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 18 of 42 i dd27 supply current, imo = 6 mhz conditions are hv dd = 2.7v, t a = 25 o c, cpu = 0.75 mhz, sysclk doubler disabled, vc1 = 0.375 mhz, vc2 = 23.44 khz, vc3 = 0.09 khz, analog power = off. slimo mode = 1. imo = 6 mhz. ? 1.1 1.5 ma i reset supply current in reset conditions are hv dd = 5.0v, -40 o c t a 85 o c. ? ? 250 a i sbi supply current in idle mode conditions are with internal slow speed oscillator, hv dd = 3.3v, -40 o c t a 85 o c, analog power = off. ? ? 750 a i sb supervised sleep current (por, lvd, sleeptimer, wdt, and voltage regulation) conditions are with internal slow speed oscillator, hv dd = 3.3v, -40 o c t a 85 o c, analog power = off. ? 2.8 3 a i sbr regulated sleep current (no por, no lvd, but with sleeptimer, wdt, and voltage regulation) conditions are with internal slow speed oscillator, hv dd = 3.3v, -40 o c t a 85 o c, analog power = off. ? ? 1 a i sbw watchdog sleep current (no por, no lvd, no sleep- timer, no voltage regulation but with wdt) conditions are with internal slow speed oscillator, hv dd = 3.3v, t a = 25 o c, analog power = off. ? 0.5 ? a i sbd deep sleep current (no por, no lvd, no sleep- timer, no voltage regulation and no wdt conditions are bypass mode on, deep sleep enabled, hv dd = 3.3v, t a = 25 o c, analog power = off. ? 0.1 ? a i sbdhv deep sleep current at hv (no por, no lvd, no sleep- timer, no voltage regulation and no wdt conditions are analog power off, deep sleep enabled, hv dd = 6v, t a = 25 o c. ? ((hv dd - 6) / 2) + 0.1 ? a v ref reference voltage (bandgap) trimmed for hv dd > 3.0v. 1.291 1.30 1.309 v v ref27 reference voltage (bandgap) trimmed for hv dd = 2.5v to 3.0v. 1.16 1.30 1.33 v 8.4 dc chip-level specifications (continued)
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 19 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.5 4.75v to 36v dc gpio specifications parameter description conditions min. typ. max. units r pu pull-up resistor 4 5.6 8k ? r pd pull-down resistor 4 5.6 8k ? v oh a a. ioh and iol are also limited by the die temper ature. see ?thermal considerations? on page 37 . high output level ioh = 10 ma, hv dd = 4.75v to 36v maximum 40 ma on even port pins (for example, p0[2], p1[0]), maximum 40 ma on odd port pins (for example, p0[3], p1[1]). 3.6 ? 5.4 v v ol a low output level iol = 25 ma, hv dd = 4.75v to 36v maximum 90 ma on even port pins (for example, p0[2], p1[0]), maximum 90 ma on odd port pins (for example, p0[3], p1[1]). ? ? 0.75 v i oh b b. odd and even port pins are regulated separately, therefore the current limit total applies separately to all odd port pins and to all even port pins. current supplied while maintaining 10% regulation 4.5v v oh 5.5v, hv dd = 4.75v to 36v. 5.5 ? ? ma v il input low level hv dd = 4.75v to 36v. ? ? 0.8 v v ih input high level hv dd = 4.75v to 36v. 2.1 ? ? v v h input hysteresis ? 60 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c in capacitive load on pins as input package and pin dependent. temp = 25 o c. ? 3.5 10 pf c out capacitive load on pins as output package and pin dependent. temp = 25 o c. ? 3.5 10 pf 8.6 3.0v to 5.0v dc gpio specifications parameter description conditions min. typ. max. units r pu pull-up resistor 4 5.6 8k ? r pd pull-down resistor 4 5.6 8k ? v oh a high output level ioh = 8 ma, hv dd = 3.0v to 3.6v maximum 30 ma on even port pins (for example, p0[2], p1[0]), maximum 30 ma on odd port pins (for example, p0[3], p1[1]). hv dd - 1.0 ? hv dd v v ol a low output level iol = 16 ma, hv dd = 3.0v to 3.6v maximum 60 ma on even port pins (for example, p0[2], p1[0]), maximum 60 ma on odd port pins (for example, p0[3], p1[1]). ? ? 0.75 v v il input low level hv dd = 3.0v to 3.6v. ? ? 0.8 v v ih input high level hv dd = 3.0v to 3.6v. 2.1 ? ? v
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 20 of 42 v h input hysteresis ? 60 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c in capacitive load on pins as input package and pin dependent. temp = 25 o c. ? 3.5 10 pf c out capacitive load on pins as output package and pin dependent. temp = 25 o c. ? 3.5 10 pf a. ioh and iol are also limited by the die temper ature. see ?thermal considerations? on page 37 . 8.7 2.5v to 3.0v dc gpio specifications parameter description conditions min. typ. max. units r pu pull-up resistor 4 5.6 8k ? r pd pull-down resistor 4 5.6 8k ? v oh a high output level ioh = 2 ma, hv dd = 2.5v to 3.0v maximum 16 ma on even port pins (for example, p0[2], p1[0]), maximum 16 ma on odd port pins (for example, p0[3], p1[1]). hv dd - 1.0 ? hv dd v v ol a low output level iol = 8 ma, hv dd = 2.5v to 3.0v maximum 40 ma on even port pins (for example, p0[2], p1[0]), maximum 40 ma on odd port pins (for example, p0[3], p1[1]). ? ? 0.75 v v il input low level hv dd = 2.5v to 3.0v. ? ? 0.8 v v ih input high level hv dd = 2.5v to 3.0v. 2.0 ? ? v v h input hysteresis ? 60 ? mv i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c in capacitive load on pins as input package and pin dependent. temp = 25 o c. ? 3.5 10 pf c out capacitive load on pins as output package and pin dependent. temp = 25 o c. ? 3.5 10 pf a. ioh and iol are also limited by the die temper ature. see ?thermal considerations? on page 37 . 8.6 3.0v to 5.0v dc gpio specifications (continued)
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 21 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.8 4.75v to 36v dc high voltage output specifications parameter description conditions min. typ. max. units v ohhv a a. ioh and iol are also limited by the die temper ature. see ?thermal considerations? on page 37 . high output level ioh = 50 ma, hv dd = 4.75v to 36v. hv dd - 2.0 ? ? v v olhv a low output level iol = 50 ma, hv dd = 4.75v to 36v. ? ? 2.0 v i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c out capacitive load on pins as output package and pin dependent. temp = 25 o c. ? ? 100 pf 8.9 2.5v to 5v dc high voltage output specifications parameter description conditions min. typ. max. units v ohhv a a. ioh and iol are also limited by the die temper ature. see ?thermal considerations? on page 37 . high output level ioh = 10 ma, hv dd = 2.5v to 5v. hv dd - 0.7 ? ? v v olhv a low output level iol = 10 ma, hv dd = 2.5v to 5v. ? ? 0.75 v i il input leakage (absolute value) gross tested to 1 a. ? 1 ? na c out capacitive load on pins as output package and pin dependent. temp = 25 o c. ? ? 100 pf
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 22 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.10 dc comparator specifications parameter description conditions min. typ. max. units v ossyn input offset voltage in synchronous mode (absolute value) ? ? 100 v v os input offset voltage in non- synchronous mode (absolute value) ? 2.5 15 mv i compsyn current consumption in synchronous mode ? 100 200 a i comp current consumption of comparator hv dd = 2.5v to 36v. ? 10 30 a i complp current consumption in low power mode hv dd = 2.5v to 36v. ? 3 10 a v in27 input voltage range hv dd = 2.5v to 5v. 0 ? hv dd v v in36 input voltage range hv dd = 5v to 36v. 0 ? 5.0 v v inlp27 input voltage range in low power mode hv dd = 2.5v to 5v. 0 ? hv dd -1.1 v v inlp36 input voltage range in low power mode hv dd = 5v to 36v. 0 ? 3.9 v 8.11 dc analog-to-digital converter specifications parameter description conditions min. typ. max. units v os input offset voltage ? ? 100 v v in input voltage range voltage on analog mux bus. 0 ? 3v hv in high voltage sense input range voltage on analog mux bus. 0 ? hv dd v r in input impedance ? 100k ? ? resolution 6 ? 12 bits inl inl error ? ? 1 lsb dnl dnl error ? ? 1/2 lsb absolute system error a a. maximum error is 11% for hv dd = 2.5v to 3.0v; consistent with v ref27 specifications. factory trimmed at adc gains of 1/4, 1, 4, 16. ? ? 0.75%
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 23 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.12 dc linear control specifications parameter description conditions min. typ. max. units v os comparator input offset voltage ? ? 100 v ratio1 attenuation resistor ratio a a. error in this parameter is included in the absolute system error. ? 4 ? ratio2 attenuation resistor ratio a ? 8 ? ratio3 attenuation resistor ratio a ? 16 ? r atten attenuator resistance ? 400k ? ? control loop reference resolution full range is 0v to v ref. ? 8 ?bits v dac loop control reference setting a 0 ? v ref v v oc1 pre-programmed over-current set point 120 150 180 mv v oc2 pre-programmed over-current set point 240 300 360 mv v oc3 pre-programmed over-current set point with vdac_cr mode = 1. 360 450 540 mv v oc4 pre-programmed over-current set point with vdac_cr mode = 1. 720 900 1080 mv 8.13 4.75v to 36v dc gate drive, linear output specifications a a. to maintain the absolute system error per table dc analog-to-digital converter specifications, the current into or out of the gate drive output must be less than 100 na. parameter description conditions min. typ. max. units v ohgd high output voltage hv dd = 5v to 36v. hv dd - 0.1 ? ? v v olgd low output voltage hv dd = 5v to 36v. ? hv dd - 5 ? v 8.14 2.5v to 5v dc gate drive, linear output specifications parameter description conditions min. typ. max. units v ohgd high output voltage ioh = 100 na, hv dd = 2.5v to 5v. hv dd - 0.1 ? ? v v olgd low output voltage iol = 100 na, hv dd = 2.5v to 5v. ? ? 1.0 v
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 24 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.15 4.75v to 36v dc gate drive, pwm output specifications parameter description conditions min. typ. max. units v ohgd high output voltage ioh = 1 a, hv dd = 4.75v to 36v. hv dd - 0.1 ? ? v v olgd low output voltage iol = 1 a, hv dd = 4.75v to 36v. ? hv dd - 5 ? v 8.16 2.5v to 5 v dc gate drive, pwm output specifications parameter description conditions min. typ. max. units v ohgd high output voltage ioh = 1 a, hv dd = 2.5v to 5v. hv dd - 0.1 ? ? v v olgd low output voltage iol = 1 a, hv dd = 2.5v to 5v. ? ? 1.0 v 8.17 dc analog mux bus specifications parameter description conditions min. typ. max. units r sw switch resistance to common analog bus hv dd 5v. hv dd = 3.3v. hv dd = 2.7v. ? ? ? 1000 1500 2000 ? ? ? ? ? ?
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 25 of 42 the following table lists guaranteed maximum and minimum specifications for the temperature range: -40 c t a 85 c. typical parameters apply at 25 c and are for design guidance only. note the bits porlev and vm in the table below refer to bits in the vlt_cr register. see the power psoc mixed-signal array technical reference manual for more information on the vlt_cr register. 8.18 dc por and lvd specifications parameter description conditions min. typ. max. units v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b vdd must be greater than or equal to 2.6v during startup, reset from the xres pin, or reset from watchdog. ? ? ? 2.46 2.82 4.55 2.50 2.95 4.70 v v v v lvd0 v lvd1 v lvd2 v lvd3 v lvd4 v lvd5 v lvd6 v lvd7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.50 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.55 0 2.92 0 3.02 3.13 4.48 4.64 4.73 4.81 2.61 a 2.99 b 3.09 3.20 4.55 4.75 4.83 4.95 a. always greater than 50 mv above v ppor (porlev=00) for falling supply. b. always greater than 50 mv above v ppor (porlev=01) for falling supply. v v v v v v v v
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 26 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.19 dc programming specifications parameter description conditions min. typ. max. units vdd iwrite supply voltage for flash write operations 2.80 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low level during programming or verify ? ? 0.8 v v ihp input high level during programming or verify 2.1 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor. ? ? 0.2 ma i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify driving internal pull-down resistor. ? ? 1.5 ma v olv output low level during programming or verify ? ? 0.75 v v ohv output high level during programming or verify hv dd = 2.5v to 5v. hv dd - 1.0 ? hv dd v v ohv36 output high level during programming or verify hv dd = 5v to 36v. 3.6 5.0 ? v flash enpb flash endurance (per block) erase/write cycles per block. 50 ? ? kcycles flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25 ,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). for the full industrial range, the user must employ a temperature sensor user module (flashtemp) and feed the result to the temperature argument before writing. refer to the flash apis application note an2015 at http://www.cypress.com under application notes for more information. erase/write cycles. 1,800 ? ? kcycles flash dr flash data retention 10 ? ? years
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 27 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.20 3.0v to 36v ac chip-level specifications parameter description conditions min. typ. max. units f imo24 internal main oscillator frequency for 24 mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 8-1b on page 16. slimo mode = 0. 23.4 24 24.6 a,b,c mhz f imo6 internal main oscillator frequency for 6 mhz trimmed for 5v or 3.3v operation using factory trim values. see figure 8-1b on page 16. slimo mode = 1. 5.85 6 6.15 a,b,c mhz f cpu1 cpu frequency (5v nominal) 0.91 24 24.6 a,b a. 4.75v < hv dd < 36v, -40c t a 70c. b. accuracy derived from internal main oscillator with appropriate trim for hv dd range. mhz f cpu2 cpu frequency (3.3v nominal) 0.91 12 12.3 b,c c. 3.0v < hv dd < 3.6v, -40c t a 70c. mhz f 48m digital psoc block frequency refer to the ac digital block speci- fications. 0 48 49.2 a,b,d d. see the individual user module data sheets for information on maximum frequencies for user modules. mhz f 24m digital psoc block frequency 0 24 24.6 b,d mhz f 1k internal low speed oscillator frequency 0.6 1 1.5 khz dc24m 24 mhz duty cycle 40 50 60 % step24m 24 mhz trim step size ?50 ?khz fout48m 48 mhz output frequency trimmed. utilizing factory trim values. 46.8 48.0 49.2 a,c mhz jitter24m1p 24 mhz period jitter (imo) peak-to-peak ? 300 ? ps jitter24m1r 24 mhz period jitter (imo) root mean squared ? ? 600 ps f max maximum frequency of signal on row input or row output ? ? 12.3 mhz t ramp supply ramp time 0 ? ? s t sbi wakeup time from idle mode ? ? 0 s t sb wakeup time from supervised sleep ? ? 30 s t sbr wakeup time from regulated sleep ? ? 30 s t sbw wakeup time from watchdog sleep ? ? 400 s t sbd wakeup time from deep sleep ? ? 3 ms
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 28 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.21 2.5v to 3.0v ac chip-level specifications parameter description conditions min. typ. max. units f imo12 internal main oscillator frequency for 12 mhz trimmed for 2.7v operation using factory trim values. see figure 8-1b on page 16. slimo mode = 0. 11.5 12 12.5 a,b mhz f imo6 internal main oscillator frequency for 6 mhz trimmed for 2.7v operation using factory trim values. see figure 8-1b on page 16. slimo mode = 1. 5.76 6 6.24 a,b mhz f cpu1 cpu frequency (2.7v nominal) 0.90 3 3.12 a a. accuracy derived from internal main oscillator with appropriate trim for hv dd range. mhz f blk27 digital psoc block frequency (2.7v nominal) refer to the ac digital block speci- fications. 0 12 12.5 a,b b. see the individual user module data sheets for information on maximum frequencies for user modules. mhz f 1k internal low speed oscillator frequency 0.6 1 1.5 khz dc12m 12 mhz duty cycle 40 50 60 % jitter12m1p 12 mhz period jitter (imo) peak-to-peak ? 340 ? ps jitter12m1r 12 mhz period jitter (imo) root mean squared ? ? 600 ps f max maximum frequency of signal on row input or row output ? ? 12.5 mhz t ramp supply ramp time 0 ? ? s 8.22 3.0v and 36v ac gpio specifications parameter description conditions min. typ. max. units f gpio gpio operating frequency normal strong mode. 0 ? 12.5 mhz trisef rise time, normal strong mode, cload = 50 pf hv dd = 4.5 to 5.25v, 10% - 90%. 3 ? 18 ns tfallf fall time, normal strong mode, cload = 50 pf hv dd = 4.5 to 5.25v, 10% - 90%. 2 ? 18 ns trises rise time, slow strong mode, cload = 50 pf hv dd = 3 to 5.25v, 10% - 90%. 10 27 ? ns tfalls fall time, slow strong mode, cload = 50 pf hv dd = 3 to 5.25v, 10% - 90%. 10 22 ? ns
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 29 of 42 figure 8-2. gpio timing diagram the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.23 2.5v to 3.0v ac gpio specifications parameter description conditions min. typ. max. units f gpio gpio operating frequency normal strong mode. 0 ? 3.12 mhz trisef rise time, normal strong mode, cload = 50 pf hv dd = 2.5 to 3.0v, 10% - 90%. 6 ? 50 ns tfallf fall time, normal strong mode, cload = 50 pf hv dd = 2.5 to 3.0v, 10% - 90%. 6 ? 50 ns trises rise time, slow strong mode, cload = 50 pf hv dd = 2.5 to 3.0v, 10% - 90%. 18 40 120 ns tfalls fall time, slow strong mode, cload = 50 pf hv dd = 2.5 to 3.0v, 10% - 90%. 18 40 120 ns tfallf tfalls tri sef tri se s 90% 10% gpio pin output voltage 8.24 ac high voltage output specifications parameter description conditions min. typ. max. units f hvo high voltage output operating frequency ? ? 1.04 mhz t rise ? ? 200 ns t fall ? ? 200 ns
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 30 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.25 ac comparator specifications parameter description conditions min. typ. max. units t rsync27 response time in synchronous mode (50 mv overdrive) hv dd = 2.5v to 3.0v. output clocked at 12 mhz. ? 84 ? ns t rsync36 response time in synchronous mode (50 mv overdrive) hv dd = 3.0v to 36v. output clocked at 24 mhz. ? 42 ? ns t r27 response time (50 mv overdrive) hv dd = 2.5v to 3.0v. ? ? 200 ns t r36 response time (50 mv overdrive) hv dd = 3.0v to 36v. ? ? 100 ns t rlp27 response time in low power hv dd = 2.5v to 3.0v ? ? 400 ns t rlp36 response time in low power hv dd = 3.0v to 36v ? ? 200 ns 8.26 ac analog-to-digital converter specifications parameter description conditions min. typ. max. units sample rate a, b a. dependent on clock frequency and bit resolution. see individual user module data sheets. b. for hv dd = 2.5v to 3.0v, sample rates are halved. bit bpen in the ac0_clk register must be set to 1. 12 bits to 6 bits at 6 mhz. 1.46 ? 93.75 ksps 8-bit sample rate b ? 23.4 ?ksps
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 31 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.27 3.0v to 36v ac digital block specifications parameter description conditions min. typ. max. units timer capture pulse width 50 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 mhz (42 ns nominal period). ? ? ns maximum frequency (capture not used) 4.75v < hv dd < 36v. ? ? 49.9 mhz maximum frequency (with or without capture) 3.0v < hv dd < 36v. ? ? 25.0 mhz counter enable pulse width 50 a ? ? ns maximum frequency (enable not used) 4.75v < hv dd < 36v. ? ? 49.9 mhz maximum frequency (with or without enable input) 3.0v < hv dd < 36v. ? ? 25.0 mhz pwm maximum frequency (enable not used) 4.75v < hv dd < 36v. ? ? 49.9 mhz maximum frequency (with or without enable input) 3.0v < hv dd < 36v. ? ? 25.0 mhz deadband kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 50 a ? ? ns disable mode 50 a ? ? ns maximum frequency 4.75v < hv dd < 36v. ? ? 49.9 mhz 3.0v < hv dd < 36v. ? ? 25.0 mhz 8.28 2.5v to 3.0v ac digital block specifications parameter description conditions min. typ. max. units timer capture pulse width 100 a a. 50 ns minimum input pulse width is based on the input synchronizers running at 12 mhz (84 ns nominal period). ? ? ns maximum frequency ? ? 12.5 mhz counter enable pulse width 100 a ? ? ns maximum frequency ? ? 12.5 mhz pwm maximum frequency ? ? 12.5 mhz deadband kill pulse width: asynchronous restart mode 20 ? ? ns synchronous restart mode 100 a ? ? ns disable mode 100 a ? ? ns maximum frequency ? ? 12.5 mhz
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 32 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.29 4.75v to 36v ac gate drive, linear output specifications parameter description conditions min. typ. max. units bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load 0.8 ? ? mhz 8.30 3.0v to 5.0v ac gate drive, linear output specifications parameter description conditions min. typ. max. units bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load 0.7 ? ? mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load 200 ? ? khz 8.31 2.5v to 3.0v ac gate drive, linear output specifications parameter description conditions min. typ. max. units bw ob small signal bandwidth, 20mv pp , 3db bw, 100pf load 0.6 ? ? mhz bw ob large signal bandwidth, 1v pp , 3db bw, 100pf load 180 ? ? khz 8.32 4.75v to 36v ac gate drive, pwm output specifications parameter description conditions min. typ. max. units f max ? ? 2 mhz t rob rise time 10% to 90%, 5v step, 100pf load ? ? 50 ns t fob fall time 10% to 90%, 5v step, 100pf load ? ? 50 ns
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 33 of 42 the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.33 3.0v to 5.0v ac gate drive, pwm output specifications parameter description conditions min. typ. max. units f max ? ? 1 mhz t rob rise time 10% to 90%, 5v step, 100pf load ? ? 130 ns t fob fall time 10% to 90%, 5v step, 100pf load ? ? 60 ns 8.34 2.5v to 3.0v ac gate drive, pwm output specifications parameter description conditions min. typ. max. units f max ? ? 0.5 mhz t rob rise time 10% to 90%, 5v step, 100pf load ? ? 360 ns t fob fall time 10% to 90%, 5v step, 100pf load ? ? 60 ns 8.35 4.75v to 36v ac external clock specifications parameter description conditions min. typ. max. units f oscext frequency 0.090 ? 25.0 mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ? ns ? power up imo to switch 150 ? ? s 8.36 3.0v to 5.0v ac external clock specifications parameter description conditions min. typ. max. units f oscext frequency with cpu clock divide by 1 a a. maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 0.090 ? 12.5 mhz f oscext frequency with cpu clock divide by 2 or greater b b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. 0.180 ? 25.0 mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ? ns ? power up imo to switch 150 ? ? s
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 34 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.37 2.5v to 3.0v ac external clock specifications parameter description conditions min. typ. max. units f oscext frequency with cpu clock divide by 1 a 0.090 ? 3.12 mhz f oscext frequency with cpu clock divide by 4 or greater b 0.180 ? 12.5 mhz ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ? ns ? power up imo to switch 150 ? ? s a. maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. if the frequency of the external clock is greater than 12 mhz, the cpu clock divider must be set to 4 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. 8.38 ac programming specifications parameter description conditions min. typ. max. units t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 20 ? ms t write flash block write time ? 20 ? ms t dsclk data out delay from falling edge of sclk hv dd > 3.6. ? ? 45 ns t dsclk3 data out delay from falling edge of sclk 3.0 hv dd 3.6. ? ? 50 ns t dsclk2 data out delay from falling edge of sclk 2.5 hv dd 3.0. ? ? 70 ns
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 35 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. 8.39 3.0v to 36v ac characteristics of i2c sda and scl pins parameter description conditions standard mode fast mode units min. max. min. max. f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? 0.6 ? s t lowi2c low period of the scl clock 4.7 ? 1.3 ? s t highi2c high period of the scl clock 4.0 ? 0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ? 0.6 ? s t hddati2c data hold time 0 ? 0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the sta ndard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ? 0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ? 1.3 ? s t spi2c pulse width of spikes are suppressed by the input filter. ?? 0 50ns
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 36 of 42 the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 36v and -40 c t a 85 c (referred to as 5v operation), 3.0v to 3.6v and -40 c t a 85 c (referred to as 3.3v operation), or 2.5v to 3.0v and -40 c t a 85 c (referred to as 2.7v operation), respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. figure 8-3. definition for timing for fast/standard mode on the i2c bus 8.40 2.5v to 3.0v ac characteristics of i2c sda and scl pins (fast mode not supported) parameter description conditions standard mode units min. max. f scli2c scl clock frequency 0 100 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? s t lowi2c low period of the scl clock 4.7 ? s t highi2c high period of the scl clock 4.0 ? s t sustai2c set-up time for a repeated start condition 4.7 ? s t hddati2c data hold time 0 ? s t sudati2c data set-up time 250 ? ns t sustoi2c set-up time for stop condition 4.0 ? s t bufi2c bus free time between a stop and start condition 4.7 ? s sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 37 of 42 9.0 thermal considerations the power psoc device can support a supply voltage up to 36v. an internal linear regulator provides the nominal 5 volts used to power the m8c processor and other internal resources. because regulating to a lower voltage generates excess heat, care must be taken to not exceed the maximum junction temperature of the psoc device when using higher supply voltages. the junction temperature depends on the ambient temper- ature, the amount of power being dissipated in the device and the thermal resistance ( ja ) of the package. in linear power psoc devices, dissipated power can be broken into four sources: the psoc core (cpu, psoc blocks and system resources), the general purpose inputs/outputs (gpio), and the gate drive outputs (gd). the equation for junction temper- ature is shown in equation 1, where ja is the thermal resis- tance of the device package. t j = t a + ja * (p core + p gpio + p gd ) equation 1 the core power dissipated in the psoc is the supply voltage (hv dd ) times the combined current of: the cpu, digital blocks, analog blocks and system resources (i dd ). the equation for the psoc core power dissipation is: p core = hv dd * i dd equation 2 the power dissipated in the psoc due to the gpio can be divided into two elements: current being sourced and current being sunk. because v ol is a relatively small value (less than 1v), the sinking current will not be a major contributor to heat in the power psoc. however, hv dd - v oh can be quite large and current sourced by gpio must be looked at carefully when using hv dd voltages greater than 5v. the equation for gpio power dissipation is shown in equation 3, where i sink is the total current being sunk by gpio pins, and i source is the total current being sourced by gpio pins. p gpio = v ol * i sink + (hv dd - v oh ) * i source equation 3 the power dissipated by the high voltage gate drives (gd0 and gd1) is divided into a current sink and current source element. with the gd pins, the (hv dd - v ohgd ) component is relatively small and the v olgd component can be large (approximately hv dd - 5v). therefore, with the gd pins, care must be taken to consider the effects of sinking currents. the equation for gd power dissipation is shown in equation 4, where i sinkgd is the total current sunk by the gd pins, and i sourcegd is the total current sourced by the gd pins. p gd = v olgd * i sinkgd + (hv dd - v ohgd ) * i sourcegd equation 4 the following figures show the effects of supply voltage and current on the temperature of the psoc. figure 9-1a shows the maximum current with a varied supply voltage at an ambient temperature of 70c and figure 9-1b shows the maximum current with a varied supply voltage at an ambient temperature of 85c. the psoc model used assumes i dd = 5ma and all other current is sourced by gpio. each curve in the figures shows the maximum i source that can be tolerated (t j remains below the maximum limit) at various supply voltages between 2.5v and 36v, for a specific package. the maximum current is clipped at 85 ma due to drive limita- tions on the gpio pins. the four package types available with linear power psoc devices are shown. thermal resistance ( ja ) for the packages can be found in section 9.1 on page 38. figure 9-1a. maximum current vs. supply voltage by package (70 o ambient) figure 9-1b. maximum current vs. supply voltage by package (85 o ambient) 0 10 20 30 40 50 60 70 80 90 0102030 hv dd i dd + i gpio 8-pin soic 32-pin mlf 16-pin soic 16-pin tssop 0 10 20 30 40 50 60 70 80 90 0102030 hv dd i dd + i gpio 8-pin soic 32-pin mlf 16-pin soic 16-pin tssop
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 38 of 42 9.2 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. 10.0 cy8c42x23 psoc device key features and ordering information the following table lists the cy8c42x23 power psoc device?s key package features and ordering codes . 9.1 thermal impedances per package package typical ja * 8 soic 186 o c/w 16 soic 124 o c/w 16 tssop 122 o c/w 32 qfn 22 o c/w * thermal resistance from silicon junction to ambient (t j = t a + power x ja ). package minimum peak temperature* maximum peak temperature 8 soic 240 o c 260 o c 16 soic 240 o c 260 o c 16 tssop 240 o c 260 o c 32 qfn 240 o c 260 o c * higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220+/-5 o c with sn-pb or 245+/-5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications. package ordering code flash (bytes) sram (bytes) temperature range power blocks digital blocks analog channel digital io pins hv gpo xres pin 8-pin soic cy8c42123-24sxi 4k 256 -40 c to +85 c2 4 2 4 0 no 8-pin soic tape and reel cy8c42123-24sxit 4k 256 -40 c to +85 c2 4 2 4 0 no 16-pin soic CY8C42223-24SXI 4k 256 -40 c to +85 c2 4 2 8 2 no 16-pin soic tape and reel CY8C42223-24SXIt 4k 256 -40 c to +85 c2 4 2 8 2 no 16-pin tssop cy8c42323-24zxi 4k 256 -40 c to +85 c2 4 2 10 2 no 16-pin tssop tape and reel cy8c42323-24zxit 4k 256 -40 c to +85 c2 4 2 10 2 no 32-pin qfn cy8c42423-24lfxi 4k 256 -40 c to +85 c 2 4 2 10 2 yes 32-pin qfn tape and reel cy8c42423-24lfxit 4k 256 -40 c to +85 c 2 4 2 10 2 yes 32-pin ocd qfn* cy8c42000-24lfxi* 4k 256 -40 c to +85 c 2 4 2 10 2 yes * this part may be used for in-circuit debugging. it is not available for production.
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 39 of 42 11.0 package diagrams figure 11-1. 8-lead (150) soic figure 11-2. 16-lead (150) soic 51-85066-*c pin 1 id 0~8 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 51-85068-*b
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 40 of 42 figure 11-3. 16-lead (4x4 mm) tssop figure 11-4. 32-lead (5x5 mm) qfn important note for information on the preferred dimensions for mounting qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . 51-85091-*a 51-85188 *a e-pad x, y for this product is 3.71 mm, 3.71 mm ( +/- 0.08 mm)
preliminary cy8c42323/cy8c4242 3 cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 41 of 42 ? cypress semiconductor corporation, 2005. the information contai ned herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embod ied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to th e user. the inclusion of cypress products in life-support systems application implies that the ma nufacturer assumes all risk of such use and in doing so indemni fies cypress against all charges. to obtain information about cypress semiconductor or psoc sales and technical support, reference the following information. cypress semiconductor corporation cypress and the cypress logo are registered trademarks of cypress semiconductor corporation and ?programmable system- on-chip,? psoc, psoc designer, and psoc express are trademarks of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. flash code protection note the following details of the flash code protec tion features on cypress semiconductor psoc devices. cypress semiconductor products meet the spec ifications contained in their particular data sheets. cypress semiconductor believe s that its psoc family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there m ay be methods, unknown to cypress semiconductor, that can br each the code protection features. any of these methods, to our knowledge, would b e dishonest and possibly illegal. neither cypress semiconductor nor any other semiconductor manufacturer can guarantee the security of thei r code. code protection does not mean that we are guaranteeing the product as "unbreakable." cypress semiconductor is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress semiconductor are committed to conti nuously improving the code protec tion features of our products. 198 champion court san jose, ca 95134 phone: 408.943.2600 web sites: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm
cy8c42323/cy8c4242 3 preliminary cy8c42123/cy8c4222 3 document 38-12034 rev. *c page 42 of 42 document history page description title: cy8c42123, cy8c42223, cy8c42323, and cy8c42423 power psoc? devices document number: 38-12034 rev. ecn no. issue date orig. of change description of change ** 339515 see ecn ari new data sheet. *a 391130 see ecn hmt update for pr3 cypress ?preliminary? requirements. (parts, pinouts, diagrams, specs., etc.) *b 394530 see ecn hmt change pin 13 to p1[0]i2c*. change pin 14 to nc. change pin 25 to dnu. *c 406740 see ecn hmt update white led application diagram. add r atten to the dc linear control specifications table. add cy corporate address on information page. implement cy standard qfn package terminology.

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